Slow data storage accesses can result in bottlenecks in integrated circuit performance. The desire for high speed, low complexity data storage is counterbalanced by a common requirement for testing circuits to be built into data storage devices. Such testing circuits can increase data storage latency.
The description above is presented as a general overview of related art in this field. and should not be construed as an admission that any of the information it contains constitutes prior art against the present patent application.